The subject of this invention is a method and an apparatus for analog-to-digital conversion using asynchronous Sigma-Delta modulation. The invention can be applied in the field of signal conversion and processing, especially of lowpass signals where the analog signal recovery is required, and also in measurement and control systems.
The method of analog-to-digital conversion using asynchronous Sigma-Delta modulation known from the U.S. Pat. No. 6,087,968 consists in that an analog signal is modulated using an asynchronous Sigma-Delta modulator, and an obtained square wave is sampled with reference frequency in the sampler, and then the obtained signal is subjected to decimation and rate reduction using the digital decimation filter, and the obtained digital signal is arranged in a sequence of digital words, suitable for further transmission or processing.
In the other method of encoding and decoding of a signal known from the patent application US 2005/0190865, the conversion of the analog signal into the square wave consisting in the modulation of the analog signal using the asynchronous Sigma-Delta modulator is shown, and the subsequent analog signal recovery on the basis of the knowledge of time instants, in which the edges of the square wave obtained on the output of the asynchronous Sigma-Delta modulator occur. The time instants of occurrences of successive edges of the square wave are measured with finite precision by the quantization of the width of subsequent pulses and the encoding of the quantization results in the quantizer designed in the form of the counter connected to the reference clock. After completing the quantization of the current pulse, the digital word obtained on the counter output is made available by the transmission to the devices where it undergoes further processing.
The analog-to-digital converter known from the U.S. Pat. No. 6,087,968 comprises the asynchronous Sigma-Delta modulator connected to the sampler that on the other hand is connected to the reference clock. The sampler output is connected to the digital decimation filter, whose output is at the same time an output of the analog-to-digital converter, whereas the asynchronous Sigma-Delta modulator comprises the adder on its input. The adder output, through the integrator, is connected to the hysteresis comparator, and the hysteresis comparator output, which is at the same time the asynchronous Sigma-Delta modulator output, is connected in the feedback loop to the inverted input of the adder.
The other apparatus for signal conversion known from the patent application US 2005/0190865 comprises the asynchronous Sigma-Delta modulator whose output is connected to the input of a counter that on the other hand is coupled to the reference clock. The output of the counter is connected to a processor with which the reference clock is also coupled.